1. Technical Field
Various embodiments presented herein relate to a semiconductor apparatuses, and more particularly, to a multi-chip semiconductor apparatuses including a plurality of semiconductor chips stacked through through-silicon vias (TSVs).
2. Related Art
Packaging technology for semiconductor apparatuses has continuously developed to satisfy demands for miniaturization and reliability of mountings. For example, the demand for miniaturization has accelerated the technology development for packages which are close to chip size. The demand for more reliable mountings has driven the importance and development of packaging technologies capable of improving the efficiency of mounting operations and the mechanical/electrical reliability after mounting.
Furthermore, as high performance electric and electronic products are required with miniaturization, various technologies for providing a high-capacity semiconductor module have been researched and developed. As a method for providing a high-capacity semiconductor module, high integration for memory chips may be used. This high integration may be realized by integrating a larger number of cells into a limited space of a semiconductor chip. However, such high integration for memory chips requires a high-level technology and a large amount of development time. For example, a fine critical dimension (CD) may be required. Therefore, improved stack technology may provide benefits in a high integration environment.